Integrated circuit device including CMOS tri-state drivers suitable for powerdown

ABSTRACT

An integrated circuit device capable of effectively shutting off the power supply in a powerdown mode. The integrated circuit device is connected to a first (ground) power supply, a second power supply that continuously provides power, and a third power supply that halts power supply during the powerdown mode. It includes a controller and a CMOS tri-state driver consisting of a series connection of a P-channel MOS transistor and an N-channel MOS transistor. The P-channel MOS transistor has its source connected to the third power supply, its backgates connected to the second power supply and its gate connected to the controller. The N-channel MOS transistor has its source and backgate connected to the first power supply, its drain connected to the drain of the P-channel MOS transistor and its gate connected to the controller. The controller controls such that the gate of the P-channel MOS transistor is maintained at a high level and the gate of the N-channel MOS transistor is maintained at a low level during the powerdown. Thus, the backgate and the gate of the P-channel MOS transistor are both pulled-up to the high level, thereby keeping the output of the CMOS tri-state driver at a high-impedance state during the powerdown mode. This makes it possible to positively prevent a leakage current, which originates from another CMOS tri-state driver having a common output terminal with the present CMOS tri-state driver, from flowing into the P-channel MOS transistor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an integrated circuit device includinga circuit for powering down by halting power supply.

2. Description of Related Art

Power saving of integrated circuit devices increases importance with thewidespread of equipment such as mobile telephones, which supplies powerto integrated circuits from a battery. To save consumption current ofthe integrated circuits, power supply to semiconductor devices can besuspended in accordance with the operating state of the equipment.

FIG. 6 shows a CMOS tri-state driver embedded in a conventionalintegrated circuit, and FIG. 7 shows an example of an output circuitusing the CMOS tri-state driver of FIG. 6. In FIG. 6, the CMOS tri-statedriver 120 consists of a P-channel MOS transistor 121 and an N-channelMOS transistor 122 which are connected in series. In FIG. 7, the outputcircuit produces an output signal Q that assumes one of the threelogical levels "H" (high), "L" (low) and "Z" (high-impedance) inresponse to a drive control signal EN and an output data signal D. Thepower supply to all the logic gates is denoted by VDD. FIG. 8 is a truthtable of the output circuit of FIG. 7.

FIG. 9 shows a CMOS level converter for converting the voltage amplitudeof an internal signal of a conventional integrated circuit. It is usedfor converting the voltage amplitude when the voltage amplitude of aninput/output signal of the integrated circuit is greater than that ofits internal signal. Using internal signals of a reduced voltageamplitude in the integrated circuit is effective to save its power. As arelevant prior art, a "Strong ARM processor" is known which is disclosedon page 121 of "HOT Chips 8-1996 Symposium Record".

In FIG. 9, DH and DL designate complementary inputs, and QH and QLdesignate complementary outputs. The "H" voltage of the input signals DHand DL is lower than the voltage supplied to P-channel MOS transistorsP1 and P2 of the level converter. Circuit constants of the P-channel MOStransistor P1 and N-channel MOS transistor N1 are set in advance suchthat when the N-channel MOS transistor N1 is brought into conduction,the potential of the output signal QL is sufficiently dropped to such alevel that brings the P-channel MOS transistor P2 into conduction.

Likewise, circuit constants of the P-channel MOS transistor P2 andN-channel MOS transistor N2 are set in advance such that when theN-channel MOS transistor N2 is brought into conduction, the potential ofthe output signal QH is sufficiently dropped to such a level that bringsthe P-channel MOS transistor P1 into conduction.

When the input signals DH and DL are placed at "H" and "L",respectively, the N-channel MOS transistor N1 is brought into conductionand the N-channel MOS transistor N2 is brought out of conduction. Thisdrops the potential of the output signal QL, and brings the P-channelMOS transistor P2 into conduction, thereby raising the potential of theoutput signal QH, and bringing the P-channel MOS transistor P1 out ofconduction. Thus, the output signal QH becomes "H", and the outputsignal QL becomes "L". In this case, the potential difference betweenthe output signals QH and QL equals the potential difference between thesource terminals of the P-channel MOS transistors and N-channel MOStransistors of the level converter. Thus, the output signals QH and QLcan be obtained with a potential difference varying from that betweenthe input signals DH and DL.

FIG. 10 is an example of a conventional output circuit combining theCMOS tri-state driver of FIG. 6 with the CMOS level converter of FIG. 9.The output circuit operates just as that of FIG. 7 except that thevoltage amplitude of the drive control signal EN and output data signalD differs from that of the output signal Q. The power to all the logicgates is supplied from an internal power supply with a voltage lowerthan VDD.

FIG. 11 shows an input/output circuit using the output circuit of FIG.7. As is well known, a plurality of such input/output circuits areusually connected together to each line of a bus, and are controlledsuch that only one of them drives the line of the bus at a time. Theinput/output circuit includes the CMOS tri-state driver 120 consistingof the P-channel MOS transistor 121 and the N-channel MOS transistor 122which are connected in series, and a controller circuit for controllingthe CMOS tri-state driver 120. The input/output circuit places, when thedrive control signal EN is "L", its output signal Q at thehigh-impedance state "Z" regardless of the level of the output datasignal D so that another input/output circuit connected to the same linecan drive its output signal Q to "H" or "L". In addition, theinput/output circuit transfers the level changes of the output signal Qas an input data signal N. The power supply to all the logic gates inthe output/input circuit is VDD.

FIG. 12 shows an input/output circuit employing the output circuit asshown in FIG. 9. The input/output circuit operates just as that of FIG.11 except that the voltage amplitude of the drive control signal EN andoutput data signal D differs from that of the output signal Q. The powerto all the logic gates is supplied from an internal power supply with avoltage lower than VDD.

FIG. 13 shows an example of a computer system configured by applyingintegrated circuits including the input/output circuits of FIG. 11. InFIG. 13, a CPU and a system control LSI share a memory and bus A, andemploy the input/output circuits as shown in FIG. 11. When the datatransfer between the CPU and memory is enabled by a control signal Bfrom the system control LSI to the CPU, the output circuits of thesystem control LSI place the bus A at high-impedance state "Z" so thatthe CPU carries out the data transfer with the memory through the bus A.In contrast, when the data transfer between the CPU and memory isdisabled by the control signal B from the system control LSI to the CPU,the output circuits of the CPU place the bus A at the high-impedancestate "Z" so that the system control LSI carries out the data transferwith the memory through the bus A.

In the computer system as shown in FIG. 13, the consumption power can begreatly reduced by shutting off the power supply to the CPU, when onlythe system control LSI and memory must be operated. The conventionalcomputer system, however, has a problem of not being able to achievesufficient power saving because of a drawback involved in theconventional CMOS tri-state drivers employed by the CPU. This will bedescribed in more detail with reference to FIG. 14 illustrating theP-channel MOS transistor 121 of FIGS. 11 and 12 which has its source andbackgate connected together to the power supply VDD and its drainconnected to a line of the bus. Shutting off the power supply of the CPU(for powering down) will drop the potential of the source, backgate anddrain of the P-channel MOS transistor 121 of the CMOS tri-state driver120. If the system control LSI supplies the bus A with a signal of logic"H" in this case, a forward current will flow through the PN junctionbetween the drain and the backgate of the P-channel MOS transistor 121of the CMOS tri-state driver 120 as shown in FIG. 14. This is becausethe power supply to CPU is interrupted during the powerdown, and hencethe source, which is connected to the power supply of the CPU, is placedat logic "L". Thus, electric charges are supplied from the outputterminal of the system control LSI to the power supply terminal of theCPU, thereby hindering the power saving. In view of this, a CMOStri-state driver disclosed in Japanese patent application laid-open No.8-307238/1996, for example, has an additional circuit for supplying theP-channel MOS transistor with a backgate potential as shown in FIG. 15to prevent the leakage current from flowing into the CPU even during thepower shutdown. Although it can prevent the forward current to flowthrough the PN junction between the drain and the backgate of theP-channel MOS transistor as shown in FIG. 15, since the gate of theP-channel MOS transistor is not supplied with charges in the powerdownmode, a channel is formed in the P-channel MOS transistor, resulting ina leakage to the power supply terminal of the CPU through the channel.In addition, a problem arises of increasing the number of components peroutput driver.

In the computer system as shown in FIG. 13, the consumption power canalso be greatly reduced by halting only the power supply to the internalcircuits of the CPU, when it is necessary to operate only the systemcontrol LSI and memory but not the CPU. In this case, the output of theCMOS tri-state driver of FIG. 10 must be placed at "Z" by supplying "H"to the gate of the P-channel MOS transistor, and "L" to the gate of theN-channel MOS transistor. However, since the power supply is halted tothe internal circuit of the CPU which delivers the complementary signalsto the pair of the input terminals of the CMOS level converters of FIG.10, the gate of the P-channel MOS transistor 121 is not supplied withthe "H" voltage, making it impossible to prevent the leakage currentfrom flowing through the channel to the power supply terminal of theCPU.

FIG. 16 shows a CMOS tri-state driver disclosed in Japanese patentapplication laid-open No. 9-64718/1997, and FIG. 17 shows a CMOStri-state driver disclosed in U.S. Pat. No. 4,963,766. To avoid leakagedue to a high voltage applied to the output terminal of the CMOStri-state driver from the output terminal of another driver, the CMOStri-state driver not only supplies a high voltage to the backgate of theP-channel MOS transistor QP1 or QP42 of FIGS. 16 and 17, but alsoincludes a circuit for raising, through the P-channel MOS transistor QP2or QP41, the gate voltage of the P-channel MOS transistor QP1 or QP42 inresponse to the high voltage applied to the output terminal to bring theP-channel MOS transistor QP1 or QP42 out of conduction. Each of the CMOStri-state drivers, however, has a problem in that the gate of theP-channel MOS transistor QP1 or QP42 is supplied with electric chargesthrough the P-channel MOS transistor QP2 or QP41 connected across theoutput terminal and the gate, and that this provides a delay whichcauses a transient leakage current to flow when the voltage applied tothe output terminal sharply rises.

SUMMARY OF THE INVENTION

The present invention is implemented to solve the foregoing problems. Itis therefore an object of the present invention to provide an integratedcircuit device capable of effectively shutting off the power supply inthe powerdown mode by eliminating the leakage.

According to a first aspect of the present invention, there is providedan integrated circuit device comprising:

a first power supply terminal to which a first fixed potential issupplied; a second power supply terminal to which a second fixedpotential is supplied; a third power supply terminal to which a thirdfixed potential that can be powered down is supplied; an outputterminal; a first conductivity type MOS transistor having its sourceconnected to the third power supply terminal, its backgate connected tothe second power supply terminal, and its drain connected to the outputterminal, the source and backgate being electrically isolated; a secondconductivity type MOS transistor having its drain connected to theoutput terminal, and its backgate and source connected to the firstpower supply terminal; a potential difference detector connected to thesecond power supply terminal and the third power supply terminal fordetecting a potential difference between them; and a gate potentialcontroller connected to the potential difference detector forcontrolling a potential of the gate of the first conductivity type MOStransistor in response to an output of the potential differencedetector.

Here, the gate potential controller may control a potential of a gate ofthe second conductivity type MOS transistor in response to the output ofthe potential difference detector.

According to a second aspect of the present invention, there is providedan integrated circuit device comprising:

a first power supply terminal to which a first fixed potential issupplied; a second power supply terminal to which a second fixedpotential is supplied; a third power supply terminal to which a thirdfixed potential that can be powered down is supplied; an outputterminal; a first conductivity type MOS transistor having its source andbackgate connected to the second power supply terminal, and its drainconnected to the output terminal; a second conductivity type MOStransistor having its drain connected to the output terminal, and itsbackgate and source connected to the first power supply terminal; apotential difference detector connected to the second power supplyterminal and the third power supply terminal for detecting a potentialdifference between them; and a CMOS level converter for convertingoutputs of the potential difference detector, and for supplying aconverted signal to at least one of a gate of the first conductivitytype MOS transistor and a gate of the second conductivity type MOStransistor.

Here, the CMOS level converter may supply, when the potential differencedetector detects the potential difference between the second powersupply terminal and the third power supply terminal, the gate of thefirst conductivity type MOS transistor with a potential equal to thepotential of the second power supply terminal, and the gate of thesecond conductivity type MOS transistor with a potential equal to thepotential of the first power supply terminal.

The CMOS level converter may comprises: a first power supply terminal towhich a first fixed potential is supplied; a second power supplyterminal to which a second fixed potential is supplied; a first datainput terminal; a second data input terminal; a first output terminal; asecond output terminal; a first mode control input terminal; a secondmode control input terminal; a first first conductivity type MOStransistor having its source connected to the second power supplyterminal, its drain connected to the first output terminal, and its gateconnected to the first mode control input terminal; a second firstconductivity type MOS transistor having its source connected to thesecond power supply terminal; its drain connected to the first outputterminal, and its gate connected to the second output terminal; a thirdfirst conductivity type MOS transistor having its source connected tothe second power supply terminal, its drain connected to the secondoutput terminal and its gate connected to the first output terminal; afirst second conductivity type MOS transistor having its drain connectedto the first output terminal, and its gate connected to the first modecontrol input terminal; a second second conductivity type MOS transistorhaving its source connected to the first power supply terminal, itsdrain connected to a source of the first second conductivity type MOStransistor, and its gate connected to the first data input terminal; athird second conductivity type MOS transistor having its sourceconnected to the first power supply terminal, its drain connected to thesecond output terminal, and its gate connected to the second modecontrol input terminal; and a fourth second conductivity type MOStransistor having its source connected to the first power supplyterminal, its drain connected to the second output terminal, and itsgate connected to the second data input terminal, wherein the first modecontrol input terminal and the second mode control input terminal may beconnected to the potential difference detector, and the first outputterminal may be connected to the gate of the first conductivity type MOStransistor.

According to a third aspect of the present invention, there is providedan integrated circuit device comprising: a first power supply terminalto which a first fixed potential is supplied; a second power supplyterminal to which a second fixed potential is supplied; a tri-statedriver including a first conductivity type MOS transistor that has asource and a backgate which are isolated from each other and has thebackgate connected to the second power supply terminal, and a secondconductivity type MOS transistor that has its drain connected to a drainof the first conductivity type MOS transistor and its source connectedto the first power supply terminal; a switching circuit for connectingor disconnecting the source of the first conductivity type MOStransistor with the second power supply terminal; a gate potentialcontroller for controlling a potential of a gate of the firstconductivity type MOS transistor; and a power supply controller forcontrolling the switching circuit and the gate potential controller,wherein the integrated circuit device is partitioned into a first blockincluding the tri-state driver, and a second block including the powersupply controller, and wherein the switching circuit disconnects, whenthe power supply controller powers down the first block, the source ofthe first conductivity type MOS transistor from the second power supplyterminal, and the gate potential controller supplies the gate of thesecond conductivity type MOS transistor with a potential equal to thepotential of the second power supply terminal.

According to a fourth aspect of the present invention, there is provideda CMOS level converter for converting an amplitude potential of asignal, the CMOS level converter comprising: a first power supplyterminal to which a first fixed potential is supplied; a second powersupply terminal to which a second fixed potential is supplied; a firstdata input terminal; a second data input terminal; a first outputterminal; a second output terminal; a first mode control input terminal;a second mode control input terminal; a first first conductivity typeMOS transistor having its source connected to the second power supplyterminal, its drain connected to the first output terminal, and its gateconnected to the first mode control input terminal; a second firstconductivity type MOS transistor having its source connected to thesecond power supply terminal; its drain connected to the first outputterminal, and its gate connected to the second output terminal; a thirdfirst conductivity type MOS transistor having its source connected tothe second power supply terminal, its drain connected to the secondoutput terminal and its gate connected to the first output terminal; afirst second conductivity type MOS transistor having its drain connectedto the first output terminal, and its gate connected to the first modecontrol input terminal; a second second conductivity type MOS transistorhaving its source connected to the first power supply terminal, itsdrain connected to a source of the first second conductivity type MOStransistor, and its gate connected to the first data input terminal; athird second conductivity type MOS transistor having its sourceconnected to the first power supply terminal, its drain connected to thesecond output terminal, and its gate connected to the second modecontrol input terminal; and a fourth second conductivity type MOStransistor having its source connected to the first power supplyterminal, its drain connected to the second output terminal, and itsgate connected to the second data input terminal.

Here, a potential of a signal supplied to the first data input terminaland the second data input terminal may differ from a potentialdifference between the first power supply terminal and the second-powersupply terminal, and a potential of a signal supplied to the first modecontrol input terminal and the second mode control input terminal mayequal the potential difference between the first power supply terminaland the second power supply terminal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an embodiment 1 of an integratedcircuit device in accordance with the present invention;

FIG. 2 is a circuit diagram showing a CMOS input/output terminal circuitin the embodiment 1;

FIG. 3 is a block diagram showing an embodiment 2 of the integratedcircuit device in accordance with the present invention;

FIG. 4 is a circuit diagram showing a potential difference detector 35of the embodiment 2;

FIG. 5 is a circuit diagram showing an input/output terminal circuit ofthe embodiment 2;

FIG. 6 is a circuit diagram showing a conventional CMOS tri-statedriver;

FIG. 7 is a circuit diagram showing a conventional output circuit;

FIG. 8 is a truth table of the conventional output circuit of FIG. 7;

FIG. 9 is a circuit diagram showing a conventional CMOS level converter;

FIG. 10 is a circuit diagram showing a conventional output circuit usingthe CMOS level converters of FIG. 9;

FIG. 11 is a circuit diagram showing an input/output circuit employingthe conventional output circuit of FIG. 7;

FIG. 12 is a circuit diagram showing an input/output circuit employingthe conventional output circuit of FIG. 10;

FIG. 13 is a block diagram showing a conventional computer system;

FIG. 14 is a cross-sectional view of a P-channel MOS transistor 121connected to the output terminal of the CMOS tri-state driver;

FIG. 15 is a circuit diagram showing a conventional CMOS tri-statedriver disclosed in Japanese patent application laid-open No.8-307238/1996;

FIG. 16 is a circuit diagram showing a conventional CMOS tri-statedriver disclosed in Japanese patent application laid-open No.9-64718/1997; and

FIG. 17 is a circuit diagram showing a conventional CMOS tri-statedriver disclosed in U.S. Pat. No. 4,963,766.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention will now be described with reference to the accompanyingdrawings.

EMBODIMENT 1

FIG. 1 is a block diagram showing an embodiment 1 of an integratedcircuit device in accordance with the present invention. In FIG. 1, aCPU 2, bus controller 3, memory 4, power switching circuit 5 and pad 6are disposed on a chip 1, and the CPU 2, bus controller 3 and memory 4are interconnected by an internal data bus 7 to carry out data transferbetween them. The CPU 2 supplies the bus controller 3 with an addresssignal 8, read/write signal 9 and access request signal 10, and the buscontroller 3 supplies the CPU 2 with an access completion signal 11, busgrant signal 12 and CPU reset signal 13, and the memory 4 with anaddress signal 14, read strobe signal 15 and write strobe signal 16.

The bus controller 3 further supplies the power switching circuit 5 witha power supply shutdown control signal 17, and the power switchingcircuit 5 supplies the CPU 2 with a power supply 18 which is haltedduring the powerdown.

From the outside of the chip 1, a power supply 19 and ground powersupply 20 supply power to the pad 6, CPU 2, bus controller 3, memory 4and power switching circuit 5. The power supplies 18 and 19 are positivewith respect to the ground power supply 20, and are identical in anormal operation mode.

The bus controller 3 supplies the pad 6 with an external address bussignal 21, external read strobe signal 22 and external write strobesignal 23, and the pad 6 supplies the bus controller 3 with a powerdownrequest signal 24 and an external data signal 25.

FIG. 2 is a circuit diagram showing a CMOS input/output terminalcircuit. It comprises a NAND circuit ND2 having its inputs connected tothe power supplies 18 and 19, and its output connected to an inverterIV2; a NAND circuit ND1 having its input connected to the output of theinverter IV2 and to an output enable signal 40 and an output data signal41; a P-channel MOS transistor 26 having its gate connected to theoutput 32 of the NAND circuit ND1, its source connected to the powersupply 18, and its backgate connected to the power supply 19; a NORcircuit NR1 having its inputs connected to the output of the NANDcircuit ND2, to the output enable signal 40 through an inverter IV1 andto the output data signal 41; an N-channel MOS transistor 27 having itsgate connected to the output 33 of the NOR circuit NR1, its drain to thedrain of the P-channel MOS transistor 26, its backgate and source to theground power supply 20; and an inverter IV3 having its input connectedto the output 29 of a CMOS tri-state driver 28. The CMOS tri-statedriver 28 consists of the P-channel MOS transistor 26 and N-channel MOStransistor 27, and its output 29 is connected to the internal data bus 7and inverter IV3 which produces the output data as input data. Here, thepower supply 18 supplies power to the NOR circuit NR1, and inverters IV1and IV3, whereas the power supply 19 supplies power to the NAND circuitsND1 and ND2, and the inverter IV2.

Next, the operation of the present embodiment 1 will be described underthe headings of the normal operation mode, a powerdown mode and a resetoperation of the powerdown mode.

(1) Normal Operation Mode.

First, the CPU 2 of FIG. 1 starts the data processing in response to theCPU reset signal 13 supplied from the bus controller 3. In this case,the bus controller 3 outputs "bus grant" ("H" (high) voltage, forexample) as the bus grant signal 12. While the bus grant signal 12indicative of the bus grant is being output, the CPU 2 takes control ofthe internal data bus 7, whereas the bus controller 3 takes control ofthe internal data bus 7 while the bus grant signal 12 indicative of businhibition is being output. In the former case, the CPU 2 outputs theaddress signal 8 indicating the head address of a program, and at thesame time outputs the read/write signal 9 indicating "read" ("H"voltage, for example), and the access request signal 10 indicative of"request" ("H" voltage, for example).

Receiving the access request signal 10 indicating the "request", the buscontroller 3 detects that an access takes place from the CPU 2. The buscontroller 3 decodes the address signal 8, and makes a decision as towhether the address indicates the memory 4 in the chip 1. If the answeris positive, the bus controller 3 outputs the address signal 8 as theaddress signal 14, and the read strobe signal 15a indicative of "readrequest" ("H" voltage, for example). The address signal 8 can indicatebesides the memory 4 an external memory connected to the chip 1, or aregister in the bus controller 3, though only the operation when theaddress signal 8 points the memory 4 will be described here for thepurpose of simplicity.

Receiving the read strobe signal 15 indicative of the "read request",the memory 4 reads data associated with the address signal 14, andsupplies the data to the internal data bus 7. The bus controller 3outputs the access completion signal 11 indicative of "completion" ("H"voltage, for example) at the time when the memory supplies the data tothe internal data bus 7, and then outputs the read strobe signal 15indicative of a "read relinquish" ("L" voltage, for example). Detectingthe access completion signal 11 indicative of the "completion", the CPU2 captures the program (data) from the internal data bus 7, and startsthe processing. Thus, the CPU 2 sequentially reads instructions of theprogram from the memory 4, and executes them. When an instructioncommands to read data from the memory 4, it captures the data from theinternal data bus 7 in the same manner as when reading the programinstructions.

In contrast, when writing data to the memory 4, the CPU 2 outputs theaddress signal 8 indicating the address of write data, and supplies theinternal data bus 7 with the write data through the CMOS input/outputterminal circuits as shown in FIG. 2. At the same time, the CPU 2supplies the bus controller 3 with the read/write signal 9 indicative of"write" ("L" voltage, for example) and the access request signal 10indicative of "request" ("H" voltage, for example).

Receiving the access request signal 10 indicating the "request", the buscontroller 3 detects that an access takes place from the CPU 2. The buscontroller 3 decodes the address signal 8, and makes a decision as towhether the address indicates the memory 4 in the chip 1. If the answeris positive, the bus controller 3 outputs the address signal 14corresponding to the address signal 8, and the write strobe signal 16aindicative of "write request" ("H" voltage, for example). Receiving thewrite strobe signal 16 indicative of the "write request", the memory 4writes the data, which is supplied through the internal data bus 7, inmemory cells associated with the address signal 14. The bus controller 3outputs the access completion signal 11 indicative of "completion" ("H"voltage, for example) at the time when the memory 4 completed the datawrite to the memory cells, and then outputs the write strobe signal 16indicative of a "write relinquish" ("L" voltage, for example). Detectingthe access completion signal 11 indicative of the "completion", the CPU2 learns that the next data transfer becomes possible using the internaldata bus 7.

Next, the operation when the bus controller 3 takes control of the buswill be described.

While the bus controller 3 outputs the bus grant signal 12 indicative ofthe "bus grant", the CPU 2 monopolizes the internal data bus 7, and thebus controller 3 does not spontaneously carry out the data transferusing the internal data bus 7.

For the bus controller 3 to take control of the internal data bus 7, itoutputs the bus grant signal 12 indicative of "bus inhibition" ("L"voltage, for example). Receiving the bus grant signal 12 indicative ofthe "bus inhibition" from the bus controller 3, the CPU 2 outputs theoutput enable signal 40 of logic "L" to place the output of the CMOSinput/output terminal circuits to "Z" (high-impedance state), therebyrelinquishing the internal data bus 7. Thus, the CPU 2 does not drivethe internal data bus 7 or supplies the bus controller 3 with the accessrequest signal 10, even if the program under the execution instructs toread or write data from or to the memory 4. Thus, the bus controller 3can carry out the data transfer using the internal data bus 7.

When the bus controller 3 reads data from the memory 4 through theinternal data bus 7, it supplies the memory 4 with the address signal14, and outputs the read strobe signal 15 indicative of the "readrequest" ("H" voltage, for example). Receiving the read strobe signal 15indicative of the "read request", the memory 4 reads data stored in thememory cells associated with the address signal 14, and supplies it tothe internal data bus 7. The bus controller 3 captures the data from theinternal data bus 7, writes the data in a register of the bus controller3, and outputs the read strobe signal 15 indicative of a "readrelinquish" ("L" voltage, for example).

When writing data to the memory 4, the bus controller 3 supplies thememory 4 with the address signal 14 and the data in its register, andoutputs the write strobe signal 16 indicative of a "write request" ("H"voltage, for example). Receiving the write strobe signal 16 indicativeof the "write request", the memory 4 writes the data supplied throughthe internal data bus 7 in the memory cells associated with the addresssignal 14. The bus controller 3 causes the access completion signal 11to generate an interrupt at the time when the memory 4 completes thedata write to the memory cells, and then outputs the write strobe signal16 indicative of the "write relinquish" ("L" voltage, for example).

(2) Operation in the Powerdown Mode.

The powerdown mode is started when the pad 6 supplies the bus controller3 with the powerdown request signal 24 indicative of a "powerdownrequest" ("H" voltage, for example). Detecting the powerdown requestsignal 24 indicative of the "powerdown request", the bus controller 3supplies the power switching circuit 5 with the power supply shutdowncontrol signal 17 indicative of "disconnection" ("H" voltage, forexample). Receiving the power supply shutdown control signal 17indicative of the "disconnection", the power switching circuit 5interrupts the supply from the power supply 18, after which theinput/output terminal circuit of the CPU 2 operates as follows.

When the power supply 18 is shut off, the NAND circuit ND2 of FIG. 2supplies the powerdown control line 30 with logic "H" (the voltage ofthe power supply 19), and the inverter IV2 supplies the powerdowncontrol line 31 with logic "L" by inverting the signal on the powerdowncontrol line 30. Here, the powerdown control lines 30 and 31 areconnected to the NAND circuit ND1 and NOR circuit NR1, respectively.Accordingly, the NAND circuit ND1 produces logic "H" from its output 32and the NOR circuit NR1 produces logic "L" from its output 33independently of the levels of the output enable signal 40 and outputdata signal 41.

Thus, the P-channel MOS transistor 26 is placed at the non-conductingstate with its gate and backgate maintained at logic "H" (the voltage ofthe power supply 19). At the same time, the N-channel MOS transistor 27is also placed at the non-conducting state with its gate, backgate andsource maintained at logic "L" (ground voltage). Thus, the outputs ofthe input/output terminal circuits of the CPU 2 are maintained at "Z"(high-impedance state) during the powerdown mode. This can positivelyprevent the current, which originates from any other input/outputterminal circuit connected together to the line of the internal data bus7, from flowing through the P-channel MOS transistor 26 into the powersupply 18 regardless of whether the memory 4 or bus controller 3 drivesthe internal data bus 7 to logic "H" or "L".

Thus, the CPU 2 places the internal data bus 7 at the high-impedancestate "Z" through the input/output terminal circuits independently ofthe internal state of the CPU 2. In the CPU 2, all the internal circuitsexcept for the input/output terminal circuits are disconnected from thepower supply 18, so that the power consumption in the CPU 2 is limitedto that due to minimum leakage current in the input/output terminalcircuits. The bus controller 3 can carry out the read/write operation tothe memory 4 as in the normal operation mode.

(3) Reset Operation of the Powerdown Mode.

Reset of the powerdown mode is started when the pad 6 supplies the buscontroller 3 with the powerdown request signal 24 indicative of"powerdown relinquish" ("L" voltage, for example). Receiving thepowerdown request signal 24 indicative of the "powerdown relinquish",the bus controller 3 supplies the power switching circuit 5 with thepower supply shutdown control signal 17 indicative of "connection" ("L"voltage, for example). Receiving the power supply shutdown controlsignal 17 indicating "connection", the power switching circuit 5 startssupplying power from the power supply 18. Since the CPU 2 does not keepits internal state in the powerdown mode, the bus controller 3 suppliesthe CPU 2 with the CPU reset signal 13 and the bus grant signal 12indicative of "bus grant". Receiving the CPU reset signal 13 and beingsupplied with the power of the power supply 18, the CPU 2 is returnedfrom the powerdown mode to the normal operation mode, and starts thedata processing.

As described above, the integrated circuit device in accordance with thepresent invention is provided with the CMOS tri-state drivers which canpositively maintain the bus at the high-impedance state "Z", that is, atthe electrically open state. This enables any circuit which is notpowered down to carry out data transfer without any extra powerconsumption, thereby making power saving possible.

EMBODIMENT 2

FIG. 3 is a block diagram showing an embodiment 2 of an integratedcircuit device in accordance with the present invention. Although thefundamental operation of the integrated circuit device is the same asthat of FIG. 1, the operation voltage of internal circuits of the CPU 2ais set lower than that of the other circuits. In FIG. 3, the referencenumeral 1a designates a chip. The chip 1a comprises a CPU 2a, buscontroller 3a, memory 4a, power switching circuit 5a and pad 6a, whichare disposed on the chip 1a. The CPU 2a, bus controller 3a and memory 4aare interconnected by an internal data bus 7a to carry out data transferbetween them. The CPU 2a supplies the bus controller 3a with an addresssignal 8a, read/write signal 9a and access request signal 10a, whereasthe bus controller 3a supplies the CPU 2a with an access completionsignal 11a, bus grant signal 12a and CPU reset signal 13a, and thememory 4a with an address signal 14a, read strobe signal 15a and writestrobe signal 16a.

The bus controller 3a further supplies the power switching circuit 5awith a power supply shutdown control signal 17a, and the power switchingcircuit 5a supplies the CPU 2a with power from a power supply 18a whichis shut off during the powerdown.

From the outside of the chip 1a, power supplies 50a and 19a and a groundpower supply 20a supply power to the pad 6a, CPU 2a, bus controller 3a,memory 4a and power switching circuit 5a. The power supplies 50a and 19aare positive with respect to the ground power supply 20, and the voltageof the power supply 50a is lower than that of the power supply 19a.

The bus controller 3a supplies the pad 6a with an external address bus21a, external read strobe signal 22a and external write strobe signal23a, whereas the pad 6a supplies the bus controller 3a with a powerdownrequest signal 24a and an external data signal 25a.

FIG. 4 is a circuit diagram showing a potential difference detector 35for detecting the shutdown of the power from the power supply 18a to theCPU 2a. By adjusting a resistor 52, the potential difference detector 35can be set such that it supplies the power down control lines 30 and 31with logic "L" and "H", respectively, in the normal operation mode,whereas with logic "H" and "L", respectively, in the powerdown mode inwhich the power supply 18a is shut off, thereby detecting the shutdownof the power supply 18a.

FIG. 5 shows an input/output terminal circuit of the CPU 2a, whichincludes a CMOS level converter. The input/output terminal circuitcomprises a NAND circuit 65 to which an enable signal 63 and a datasignal 64 are input; a CMOS level converter 70 which is supplied withthe output of the NAND circuit 65 and its inverted signal through aninverter 66; a P-channel MOS transistor 61 with its gate connected tothe output QH of the CMOS level converter 70, its source and backgateconnected to the power supply 19a; a NOR circuit 68 which is suppliedwith the data signal 64 and the enable signal through an inverter 67; aCMOS level converter 80 which is supplied with the output of the NORcircuit 68 and its inverted signal through an inverter 69; and anN-channel MOS transistor 62 with its gate connected to the CMOS levelconverter 80, its drain connected to the drain of the P-channel MOStransistor 61, and its source and backgate connected to the ground powersupply 20a. The P-channel MOS transistor 61 and N-channel MOS transistor62 constitute a CMOS tri-state driver 60 whose output data is suppliedto the internal data bus 7a, and to the CPU 2a through an inverter 90 asthe input data.

The CMOS level converter 70 and 80 each comprise a first power supplyterminal 85 to which a first fixed potential (ground power supply) 20ais supplied; a second power supply terminal 86 to which a second fixedpotential 19a is supplied; a first data input terminal 76; a second datainput terminal 77; a first output terminal 74; a second output terminal75; a first mode control input terminal 78; a second mode control inputterminal 79; a first P-channel MOS transistor 71 having its sourceconnected to the second power supply terminal 86, its drain connected tothe first output terminal 74, and its gate connected to the first modecontrol input terminal 78; a second P-channel MOS transistor 72 havingits source connected to the second power supply terminal 86, its drainconnected to the first output terminal 74, and its gate connected to thesecond output terminal 75; a third P-channel MOS transistor 73 havingits source connected to the second power supply terminal 86, its drainconnected to the second output terminal 75 and its gate connected to thefirst output terminal 74; a first N-channel MOS transistor 81 having itsdrain connected to the first output terminal 74, and its gate connectedto the first mode control input terminal 78; a second N-channel MOStransistor 82 having its source connected to the first power supplyterminal 85, its drain connected to a source of the first N-channel MOStransistor 81, and its gate connected to the first data input terminal76; a third N-channel MOS transistor 83 having its source connected tothe first power supply terminal 85, its drain connected to the secondoutput terminal 75, and its gate connected to the second mode controlinput terminal 79; and a fourth N-channel MOS transistor 84 having itssource connected to the first power supply terminal 85, its drainconnected to the second output terminal 75, and its gate connected tothe second data input terminal 77.

Next, the operation of the present embodiment 2 will be described.

In the normal mode operation, the potential difference detector 35supplies the powerdown control lines 30 and 31 with logic "L" and "H",respectively. Thus, the P-channel MOS transistor 71 and N-channel MOStransistor 83 are brought out of conduction, whereas the N-channel MOStransistor 81 is brought into conduction, and hence the CMOS levelconverter 70 becomes just as the conventional CMOS level converter asshown in FIG. 9, and operates likewise.

In contrast, in the powerdown mode, the potential difference detector 35supplies the powerdown control lines 30 and 31 with logic "H" and "L",respectively. This brings the N-channel MOS transistor 83 intoconduction, and hence brings the P-channel MOS transistor 72 intoconduction. Accordingly, the output QH of the CMOS level converter 70 ismaintained at logic "H", whereas the output of QL of the CMOS levelconverter 80 is held at logic "L". Thus, both the P-channel MOStransistor 61 and N-channel MOS transistor 62 of the CMOS tri-statedriver 60 are brought out of conduction regardless of the state of theenable signal 63 and data signal 64, thereby maintaining thehigh-impedance state "Z".

As described above, the integrated circuit device in accordance with thepresent invention is provided with the CMOS level converters that canpositively maintain the outputs of the CMOS tri-state drivers which areconnected to the bus at the high-impedance state "Z", that is, at theelectrically open state. This makes it possible for the circuit which isnot powered down to carry out data transfer without any extra powerconsumption, thereby enabling power saving.

What is claimed is:
 1. An integrated circuit device comprising:a first power supply terminal to which a first fixed potential is supplied; a second power supply terminal to which a second fixed potential is supplied, a third power supply terminal to which a third fixed potential that can be powered down is supplied; an output terminal; a first conductivity type MOS transistor having its source connected to said third power supply terminal, its backgate connected to said second power supply terminal, and its drain connected to said output terminal; a second conductivity type MOS transistor having its drain connected to said output terminal, and its backgate and source connected to said first power supply terminal; a potential difference detector connected to said second power supply terminal and said third power supply terminal for detecting a potential difference between them, and a gate potential controller connected to said potential difference detector for controlling a potential of the gate of said first conductivity type MOS transistor in response to an output of said potential difference detector.
 2. The integrated circuit device as claimed in claim 1, wherein said gate potential controller controls a potential of a gate of said second conductivity type MOS transistor in response to the output of said potential difference detector.
 3. An integrated circuit device comprising:a first power supply terminal to which a first fixed potential is supplied; a second power supply terminal to which a second fixed potential is supplied; a tri-state driver including a first conductivity type MOS transistor that has a source and a backgate which are isolated from each other and has said backgate connected to said second power supply terminal, and a second conductivity type MOS transistor that has its drain connected to a drain of said first conductivity type MOS transistor and its source connected to said first power supply terminal; a switching circuit for connecting or disconnecting said source of said first conductivity type MOS transistor with said second power supply terminal; a gate potential controller for controlling a potential of a gate of said first conductivity type MOS transistor; and a power supply controller for controlling said switching circuit and said gate potential controller, wherein said integrated circuit device is partitioned into a first block including said tri-state driver, and a second block including said power supply controller, and wherein said switching circuit disconnects, when said power supply controller powers down said first block, said source of said first conductivity type MOS transistor from said second power supply terminal, and said gate potential controller supplies the gate of said second conductivity type MOS transistor with a potential equal to the potential of said second power supply terminal. 